Analog Circuit Design: Smart Data Converters, Filters on - download pdf or read online

By Michiel Steyaert, Herman Casier, Arthur H. M. van Roermund

ISBN-10: 9048130824

ISBN-13: 9789048130825

Analog Circuit layout includes the contribution of 18 tutorials of the 18th workshop on Advances in Analog Circuit layout. each one half discusses a particular to-date subject on new and helpful layout principles within the region of analog circuit layout. every one half is gifted through six specialists in that box and cutting-edge details is shared and overviewed. This booklet is quantity 18 during this winning sequence of Analog Circuit layout, delivering worthwhile info and perfect overviews of: clever facts Converters: Chaired through Prof. Arthur van Roermund, Eindhoven collage of expertise, Filters on Chip: Chaired via Herman Casier, AMI Semiconductor Fellow, Multimode Transmitters: Chaired by way of Prof. M. Steyaert, Catholic collage Leuven, Analog Circuit layout is an important reference resource for analog circuit designers and researchers wishing to maintain abreast with the newest improvement within the box. the educational insurance additionally makes it compatible to be used in a complicated layout.

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Extra info for Analog Circuit Design: Smart Data Converters, Filters on Chip, Multimode Transmitters

Sample text

G. [35]). For designs with wideband inputs, it is conceivable to measure and calibrate the mismatch [36]. Alternatively, it is possible to merge the sampling operation for the two paths into a single circuit [37]. 5 Flip-Around Charge Redistribution Beyond reducing the number of amplifiers in the pipeline, the next step is to improve the efficiency of the circuit at the transistor level. A widely used idea is to employ “flip-around” charge redistribution [38]. 5-bit pipeline stage that uses this technique is shown in Fig.

In the remainder of this paper, a novel charge-sharing SAR architecture will be presented that focuses on these aspect for the realization of lowpower ADCs. 3 Charge-Sharing Successive Approximation ADC Architecture The SAR ADC topology proposed does not need any high-speed buffers. Instead of operating in the voltage-domain, the useful signal is represented by charge. Its operation is explained in the following steps [10, 11]. 1 Input Sampling An accurate charge proportional to the input signal must be created, and the most obvious way is of course to sample the input voltage on a capacitor.

It remains to be seen if these issues can be handled efficiently in practice. Improving supply rejection, for instance, could be achieved using voltage regulators. This is custom practice in other areas of mixedsignal design, as for example clock generation circuits [58]. Especially when the power of the ADC’s critical core circuitry is lowered significantly, implementing supply regulation should be justifiable. 2 Low-Power Pipelined A/D Conversion 33 Analog Nonlinearity Vin Σ Backend A/D g – A/D Σ D/A Coefficient Estimation MOD Dout Σ g–1 Digital Inverse Fig.

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Analog Circuit Design: Smart Data Converters, Filters on Chip, Multimode Transmitters by Michiel Steyaert, Herman Casier, Arthur H. M. van Roermund

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